Some tricks which i got from linux makefile

I'm not superuser of make, but sometime i use it. My knowledge about the files usually end in the next things: I know that if I'll create Makefile file, write some simple rules which are in general form:

And than execute make target, it executes command. Last time ago i started to learn some low-level stuffs as assembly programming, operating system theory and practice (as you can read and understand from previous blog posts about assembly programming). Some days ago i started to read Linux kernel Makefile and here i want to share some make syntax features which i learned from there. So this post is not for people who used make much time and knows much about it.


origin - is a builtin function which returns information about variable. It's general form is:

You can pass any $(variable) to it and it will return info about it. Return value of origin can be:
  • undefined - variable didn't defined
  • default - default var, like $(CC) and etc...
  • environemnt - from environment
  • environment override - return environemnt which was overridden with make -e
  • file - from makefile
  • command line - from make command line arguments
  • automatic - see bellow
So we can use it like this:


Usually makefile prints every action after executing it, but sometimes we no need in it. We can use @ prefix for it, for example:

In this way make will not print @echo "Done." line, but just prints Done.


filter function removes all space separated words from text, which doesn't match no one template. General view of it:

For example, we have targets list and we need to check is there build target there or not:

Check empty value

We can check empty value with following:

Current directory

Previously when i was need to get current directory path, i used something like this:

Now i know about builtin variable:

Errors, Warning and Info

There are 3 builtin functions for printing errors, warning and info:


VPATH variable defines list of directories where template rules will search dependencies:

Automatic variables

There are some special macros:
  • $| - Names of all the order-only prerequisites, with spaces between them
  • $@ - Filename of the target of the rule
  • $? - Names of all the prerequisites that are newer than the target
  • $< - Name of the first prerequisite


This is all. If you will have any question or suggestions, please write me a comment or ping me in twitter.

English is not my first language, so you'll find mistakes in blog post please write me in comments or drop me email .


Unknown said…
I can't see any of the examples fwiw. I'm on mobile, maybe that's related